1. Field of the Invention
The invention relates in general to a method of fabricating an electrostatic discharge (ESD) protection device. More particularly, this invention relates to a method of fabricating a self-aligned silicide (salicide) layer in an electrostatic discharge protection device.
2. Description of the Related Art
In a conventional electrostatic discharge protection device, if a salicide layer is formed on the drain region thereof, the electrostatic current is easily localized to cause the junction to be locally burned and damaged. Once the junction is damaged, the protection function can never be achieved. To solve such problem, a method using salicide layer is provided and shown in FIG. 1A to FIG. 1C.
In FIG. 1A, on a substrate 100 having a shallow trench isolation 102, a gate 104, a source region 106a and a drain region 106b are formed. A salicide block layer 108 is formed to cover the gate 104, the source region 106a and the drain region 106b. A mask layer 110 is formed to cover the salicide block layer 108 on the drain region 106b. To ensure the salicide block layer 108 covering the drain region 106b is completely covered, it is often that the salicide block layer 108 is formed to cover a portion of the gate 104 next to the drain region 106b. Typically, according to the design rule, the width of the gate to be covered with the mask layer 110 is about 0.3 micron.
In FIG. 1B, the exposed salicide block 108 layer is removed to expose the source region 106a and a portion of the gate 104, while the drain region 106b is still covered with the remaining salicide block layer 108a. In FIG. 1C, a salicide layer 112 is formed on the exposed source region 106a and a portion of the gate 104. As shown in FIG. 1C, the drain region 106b is free from formation of the salicide layer 112 for being covered with the salicide block layer 108a. Therefore, when the device approaches a second breakdown, the ballast resistance of the drain region 106b prevents current localization, and thus, prevents the junction from being damaged thereby. However, as a portion of the gate 104 is also covered with the salicide block layer 108 while forming the salicide layer 112, the resistance of the gate 104 is thus remained at a certain high magnitude. As the integration of the integrated circuit increases, the line width of the gate consequently shrinks, the high resistance of the gate more and more seriously affects the electrical performance of the device.
In a typical conventional electrostatic discharge protection integrated circuit (IC), I/O driving transistors are connected with electrostatic discharge protection transistors in parallel. When electrostatic discharge occurs, the I/O driving transistors are switched to function as the electrostatic discharge protection transistors to share the electrostatic discharge current. Therefore, for these I/O driving transistors, in addition to protecting the junction from being damaged, it is also important to maintain the IC speed, such that the performance of the devices does not deteriorate. With the conventional method, since the salicide layer can only be formed on a portion of the gate, this requirement can hardly be met.